1. Field of the Invention
The present invention relates generally to semiconductor devices and methods, and more particularly, to a semiconductor device having an electrostatic discharge (ESD) protection structure.
2. Description of the Related Art
When a semiconductor device is exposed to an electric field, an electric potential may exist between the semiconductor device and other devices. When the electric potential exceeds a given voltage, an electrostatic discharge (ESD) may occur. The ESD may flow into the semiconductor device, which may cause damage to the semiconductor device.
FIG. 1 illustrates a plan view of a Printed Circuit Board (PCB) according to conventional methods. As shown, PCB 20 may be packaged in a semiconductor package 10. The semiconductor package 10 may include a semiconductor chip 12 mounted on the PCB 20. The PCB 20 may include conductive patterns 24 and external connection terminals 22. The external connection terminals 22 may be formed along an edge of the PCB 20 and may be coupled to the conductive patterns 24.
The conductive patterns 24 may be formed close to the outer layer of the PCB 20 by conventional methods. The conductive patterns 24 may be conductive paths through which an ESD charge 30 may flow into the PCB 20, and the ESD charge 30 may further flow into the semiconductor chip 12, which may be mounted on the PCB 20. The conductive patterns 24 may not be formed in the outer layer of the PCB 20 in order to help prevent the ESD charge 30 from reaching the semiconductor chip 12. However, forming conductive patterns 24 away from the outer layer of the PCB 20 may cause various problems. These problems may include a decrease in mounting density, a warping of the PCB 20, and/or a reduction in heat dissipation.
By other conventional methods, passive, insulating devices with high impedance may be formed in the semiconductor package 10 and/or the PCB 20. However, this may increase the fabrication cost of the semiconductor package 10, increase fabrication complexity, reduce the yield of the semiconductor device, reduce the device mounting area, and/or decrease the mounting density.